Invention Application
- Patent Title: VIA STRUCTURE FOR SEMICONDUCTOR DIES
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Application No.: US17748817Application Date: 2022-05-19
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Publication No.: US20220285299A1Publication Date: 2022-09-08
- Inventor: Yaoyu PANG , Steven A. ATHERTON
- Applicant: Cirrus Logic International Semiconductor Ltd.
- Applicant Address: GB Edinburgh
- Assignee: Cirrus Logic International Semiconductor Ltd.
- Current Assignee: Cirrus Logic International Semiconductor Ltd.
- Current Assignee Address: GB Edinburgh
- Main IPC: H01L23/00
- IPC: H01L23/00

Abstract:
A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.
Information query
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