Invention Application
- Patent Title: MICROELECTRONIC DEVICES WITH ISOLATION TRENCHES IN UPPER PORTIONS OF TIERED STACKS, AND RELATED METHODS
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Application No.: US17804958Application Date: 2022-06-01
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Publication No.: US20220302215A1Publication Date: 2022-09-22
- Inventor: Yi Hu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: H01L27/24
- IPC: H01L27/24 ; H01L25/065 ; H01L21/02 ; H01L21/8238 ; H01L21/768 ; H01L27/112

Abstract:
Methods for forming microelectronic devices include forming lower and upper stack structures, each comprising vertically alternating sequences of insulative and other structures arranged in tiers. Lower and upper pillar structures are formed to extend through the lower and upper stack structures, respectively. An opening is formed through the upper stack structure, and at least a portion of the other structures of the upper stack are replaced by (e.g., chemically converted into) conductive structures, which may be configured as select gate structures. Subsequently, a slit is formed, extending through both the upper and lower stack structures, and at least a portion of the other structures of the lower stack structure are replaced by a conductive material within a liner to form additional conductive structures, which may be configured as access lines (e.g., word lines). Microelectronic devices and structures and related electronic systems are also disclosed.
Public/Granted literature
- US11925037B2 Microelectronic devices with isolation trenches in upper portions of tiered stacks, and related methods Public/Granted day:2024-03-05
Information query
IPC分类: