Invention Application
- Patent Title: PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
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Application No.: US17657856Application Date: 2022-04-04
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Publication No.: US20220334865A1Publication Date: 2022-10-20
- Inventor: Roberto Colombo , Vivek Mohan Sharma
- Applicant: STMicroelectronics Application GMBH , STMicroelectronics International N.V.
- Applicant Address: DE Aschheim-Dornach; CH Geneva
- Assignee: STMicroelectronics Application GMBH,STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics Application GMBH,STMicroelectronics International N.V.
- Current Assignee Address: DE Aschheim-Dornach; CH Geneva
- Priority: IT102021000009683 20210416
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F11/07

Abstract:
A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.
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