Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system may identify, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system may generate one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system may then correct the set of bits based on the candidate set of bits identified as error-free.