Invention Application
- Patent Title: METHOD FOR OPTIMIZING FLOOR PLAN FOR AN INTEGRATED CIRCUIT
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Application No.: US17875139Application Date: 2022-07-27
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Publication No.: US20220366118A1Publication Date: 2022-11-17
- Inventor: Yi-Lin CHUANG , Shi-Wen TAN , Song LIU , Shih-Yao LIN , Wen-Yuan FANG
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. , TSMC NANJING COMPANY LIMITED
- Applicant Address: TW Hsinchu; CN Nanjing
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.,TSMC NANJING COMPANY LIMITED
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.,TSMC NANJING COMPANY LIMITED
- Current Assignee Address: TW Hsinchu; CN Nanjing
- Priority: CN202010996475.6 20200921
- Main IPC: G06F30/392
- IPC: G06F30/392 ; G06F30/373 ; G06F30/398 ; G06F30/394

Abstract:
A method is provided and includes several operations: forming a first group of macros in a first region, wherein the first group of macros are aligned with a first boundary of a channel that is coupled thereto through pins of the first group of macros; forming a second group of macros in the first region to align with a second boundary of the channel that is coupled thereto through pins of the second group of macros, wherein the first and second groups of macros are coupled to a first register; and forming a third group of macros in a second region different from the first region. A first macro and a second macro that are in the third group of macros are aligned with the first and second boundaries respectively. The third group of macros are coupled to a second register different from the first register.
Public/Granted literature
- US11893334B2 Method for optimizing floor plan for an integrated circuit Public/Granted day:2024-02-06
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