Invention Application
- Patent Title: MEMORY ADDRESS PROTECTION
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Application No.: US17825352Application Date: 2022-05-26
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Publication No.: US20220382629A1Publication Date: 2022-12-01
- Inventor: Peter John Waldemar Graumann
- Applicant: Microchip Technology Inc.
- Applicant Address: US AZ Chandler
- Assignee: Microchip Technology Inc.
- Current Assignee: Microchip Technology Inc.
- Current Assignee Address: US AZ Chandler
- Main IPC: G06F11/10
- IPC: G06F11/10

Abstract:
A method for memory protection includes receiving a burst-write instruction that includes data and a burst-write address. The data are segmented into a plurality of data blocks. One or more bits of the burst-write address, or a hash of the burst-write address are concatenated to respective data blocks to obtain data-and-write-address-bit (DWAB) segments. A SECDED ECC is executed on respective DWAB segments to generate a corresponding plurality of sets of parity bits (DWAB-PB). Respective DWAB-PB are concatenated to the corresponding data block to generate corresponding forward-error-correction (FEC) blocks, none of the FEC blocks including the burst-write address or the hash of the burst-write address. A burst-write command and a respective portion of a respective FEC block is sent to respective memory devices during a plurality of beats until all of the beats of the burst-write have been sent.
Public/Granted literature
- US11663076B2 Memory address protection Public/Granted day:2023-05-30
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