Invention Application
- Patent Title: Cache for Storing Coherent and Non-Coherent Data
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Application No.: US17331806Application Date: 2021-05-27
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Publication No.: US20220382679A1Publication Date: 2022-12-01
- Inventor: Jamshed Jalal , Bruce James Mathewson , Tushar P Ringe , Sean James Salisbury , Antony John Harris
- Applicant: Arm Limited
- Applicant Address: GB Cambridge
- Assignee: Arm Limited
- Current Assignee: Arm Limited
- Current Assignee Address: GB Cambridge
- Main IPC: G06F12/0815
- IPC: G06F12/0815 ; G06F12/0895

Abstract:
The present disclosure advantageously provides a system cache and a method for storing coherent data and non-coherent data in a system cache. A transaction is received from a source in a system, the transaction including at least a memory address, the source having a location in a coherent domain or a non-coherent domain of the system, the coherent domain including shareable data and the non-coherent domain including non-shareable data. Whether the memory address is stored in a cache line is determined, and, when the memory address is not determined to be stored in a cache line, a cache line is allocated to the transaction including setting a state bit of the allocated cache line based on the source location to indicate whether shareable or non-shareable data is stored in the allocated cache line, and the transaction is processed.
Public/Granted literature
- US11599467B2 Cache for storing coherent and non-coherent data Public/Granted day:2023-03-07
Information query
IPC分类: