Invention Application
- Patent Title: METHOD OF SEMICONDUCTOR LAYOUT WITH DIFFERENT ROW HEIGHTS
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Application No.: US17884293Application Date: 2022-08-09
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Publication No.: US20220384417A1Publication Date: 2022-12-01
- Inventor: Hui-Zhong ZHUANG , Xiang-Dong CHEN , Lee-Chung LU , Tzu-Ying LIN , Yung-Chin HOU
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L27/02
- IPC: H01L27/02 ; G06F30/392 ; H01L27/092 ; H01L23/528
Abstract:
A method includes disposing a first power rail, a second power rail and a third power rail arranged in order; disposing a first cell row having a first row height between the first power rail and the second power rail; and disposing a second cell row having the first row height between the third power rail and the second power rail. Each of the first power rail and the third power rail has a first width, and the second power rail has a second width larger than the first width.
Information query
IPC分类:
