A display device includes: a first pixel transistor couples one electrode of holding capacitance to a first signal line; a second pixel transistor couples another electrode of the holding capacitance to a second signal line; a third pixel transistor couples the other electrode of the holding capacitance to a GND potential; and a driver that supplies a negative potential to the second signal line when the first signal line is supplied with a positive potential, supplies the GND potential to the second signal line when the first signal line is supplied with the GND potential, and supplies the positive potential to the second signal line when the first signal line is supplied with the negative potential. The first and second pixel transistors are on during a writing period and off during a holding period. The third pixel transistor is off during the writing period and on during the holding period.