Invention Publication
- Patent Title: METHOD OF PRODUCING AN INTEGRATED CIRCUIT CHIP INCLUDING A BACK-SIDE POWER DELIVERY NETWORK
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Application No.: US18048005Application Date: 2022-10-19
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Publication No.: US20230142597A1Publication Date: 2023-05-11
- Inventor: Anabela Veloso , Eric Beyne , Anne Jourdain
- Applicant: IMEC VZW
- Applicant Address: BE Leuven
- Assignee: IMEC VZW
- Current Assignee: IMEC VZW
- Current Assignee Address: BE Leuven
- Priority: EP 203706.3 2021.10.20
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/66 ; H01L21/78

Abstract:
A method of producing an IC chip is provided. In one aspect, deep trenches are formed in a semiconductor layer that forms the top layer of a device wafer, the trenches going through the complete thickness of the layer. The trenches are filled with a sacrificial material, that is etched back and covered with a capping layer, thereby forming sacrificial buried rails. After processing active devices on the front surface of the semiconductor layer, including connections to the sacrificial rails, the device wafer is bonded face down to a carrier wafer, and thinned from the back side, until the sacrificial rails are exposed. The sacrificial material and the capping layer are removed and replaced by a conductive material, thereby forming the actual buried power rails. A back side power delivery network supplies power through the buried rails to the active devices of the IC. Using a sacrificial material for the buried rails can enable a wider choice of materials for these buried rails.
Information query
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