The present disclosure relates to processors, universal flash storage (UFS) control methods, and computer systems. One example processor includes a first processor core, a second processor core, a host controller register (HCI), and a service delivery subsystem (SDS). The HCI includes a first extended doorbell register and a second extended doorbell register. The first processor core may invoke, by using the first extended doorbell register, the HCI to provide first instruction information for the SDS, and the second processor core may invoke, by using the second extended doorbell register, the HCI to provide second instruction information for the SDS.