- 专利标题: CREATION OF REDUCED FORMAL MODEL FOR SCALABLE SYSTEM-ON-CHIP (SOC) LEVEL CONNECTIVITY VERIFICATION
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申请号: US18076007申请日: 2022-12-06
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公开(公告)号: US20230177244A1公开(公告)日: 2023-06-08
- 发明人: Prasun Das , Pratik Mahajan , Alfred Koelbl , Henna Arora
- 申请人: Synopsys, Inc.
- 申请人地址: US CA Mountain View
- 专利权人: Synopsys, Inc.
- 当前专利权人: Synopsys, Inc.
- 当前专利权人地址: US CA Mountain View
- 主分类号: G06F30/3323
- IPC分类号: G06F30/3323 ; G06F30/323
摘要:
A method of verifying connectivity in a circuit design, includes, in part, receiving a netlist of the circuit design; designating a plurality of destination nodes associated with the netlist; for each of the plurality of destination nodes, identifying one or more source nodes that are traversed from the destination node; for each source node identified as traversed from the destination node: transforming the netlist by including a first multiplexer having a first input terminal receiving a first variable logic value and an output terminal coupled to the source node; and enabling the first multiplexer to pass the first variable value to the destination node from the source node in order to check for connectivity between the source node and the destination node.
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