A device is disclosed, including a latch circuit, a first pass-gate transistor, and a second pass-gate transistor. The latch circuit stores a bit data and is arranged in a first layer. The first pass-gate transistor and the second pass-gate transistor are arranged in a second layer separated from the first layer. The first pass-gate transistor is coupled between a first bit line and a first terminal of the latch circuit, and the second pass-gate transistor is coupled between a second bit line and a second terminal of the latch circuit.