The present disclosure refers to integrated circuits and static random access memories. In an embodiment, an integrated circuit includes a first n-type metal oxide semiconductor (NMOS) region, a second NMOS region, a first p-type MOS (PMOS) region between the first NMOS region and the second NMOS region, a second PMOS region between the first PMOS region and the second NMOS region, and a first active bridge extending in a first direction and coupling the first NMOS region to the first PMOS region. A level of the first active bridge matches levels of the first electrode of the first pass transistor, the second electrode of the first pass transistor, the first electrode of the first pull-down transistor, the second electrode of the first pull-down transistor, the first electrode of the first pull-up transistor, and the second electrode of the first pull-up transistor.