发明公开
- 专利标题： SEMICONDUCTOR DEVICE, BATTERY PROTECTION CIRCUIT, AND POWER MANAGEMENT CIRCUIT
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申请号： US18181332申请日： 2023-03-09
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公开(公告)号： US20230215940A1公开(公告)日： 2023-07-06
- 发明人: Kouki YAMAMOTO , Haruhisa TAKATA
- 申请人： Nuvoton Technology Corporation Japan
- 申请人地址： JP Kyoto
- 专利权人： Nuvoton Technology Corporation Japan
- 当前专利权人： Nuvoton Technology Corporation Japan
- 当前专利权人地址： JP Kyoto
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L27/088 ; H02J7/00 ; H01L29/417 ; H01L29/423
摘要：
A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.
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