A semiconductor device includes a cell region including a plurality of memory cells, and a peripheral circuit region controlling the plurality of memory cells. Each of the plurality of memory cells includes a first active region and a second active region adjacent to each other, a first channel layer and a second channel layer extending in the first direction, connected to the first active region and the second active region, and separated from each other in the third direction, a first ferroelectric layer and a first gate electrode layer sequentially provided on the first channel layer, and a second ferroelectric layer and a second gate electrode layer sequentially provided on the second channel layer. The first gate electrode layer and the second gate electrode layer are separated from each other in the third direction.