An input/output circuit of a nonvolatile memory device and a nonvolatile memory device. The input/output circuit of a nonvolatile memory device includes a driver, which is configured to output data from the nonvolatile memory device to a data line, and a power gating circuit, which is connected between the driver and a power terminal or between the driver and a ground terminal and configured to block a leakage current of the driver. The power gating circuit includes a plurality of transistors electrically connected in parallel and having threshold voltages of different magnitudes, respectively.