Invention Application
- Patent Title: SEMICONDUCTOR PACKAGE AND FORMATION METHOD THEREOF
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Application No.: US18090918Application Date: 2022-12-29
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Publication No.: US20230137800A1Publication Date: 2023-05-04
- Inventor: Xuhui PENG , Kerui XI , Tingting CUI , Feng QIN , Jie ZHANG
- Applicant: Shanghai Tianma Micro-Electronics Co., Ltd. , Shanghai AVIC OPTO Electronics Co.,Ltd.
- Applicant Address: CN Shanghai; CN Shanghai
- Assignee: Shanghai Tianma Micro-Electronics Co., Ltd.,Shanghai AVIC OPTO Electronics Co.,Ltd.
- Current Assignee: Shanghai Tianma Micro-Electronics Co., Ltd.,Shanghai AVIC OPTO Electronics Co.,Ltd.
- Current Assignee Address: CN Shanghai; CN Shanghai
- Priority: CN202010393854.6 20200511
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L21/56 ; H01L23/498 ; H01L23/00

Abstract:
A semiconductor package includes a semiconductor element, a wiring structure, an encapsulation structure, and a solder ball. The semiconductor element includes a plurality of pins. A side of the wiring structure is electrically connected to the plurality of pins of the semiconductor element. The wiring structure includes at least two first wiring layers. A first insulating layer is disposed between adjacent two first wiring layers of the at least two first wiring layers. The first insulating layer includes a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The encapsulation structure at least partially surrounds the semiconductor element. The solder ball is located on a side of the wiring structure away from the semiconductor element. The solder ball is electrically connected to the at least two first wiring layers.
Public/Granted literature
- US12057324B2 Semiconductor package having a semiconductor element and a wiring structure Public/Granted day:2024-08-06
Information query
IPC分类: