An array substrate is provided. The array substate includes a base substrate; a semiconductor material layer on the base substrate; and a plurality of voltage supply lines on a side of the semiconductor material layer away from the base substrate. In a respective subpixel, the semiconductor material layer includes an active layer of a third transistor, an active layer of a fifth transistor, an active layer of a driving transistor, and a third node portion that is connected to the active layer of the third transistor, the active layer of the fifth transistor, and the active layer of the driving transistor in the respective subpixel. At least 30% of an orthographic projection of the third node portion on the base substrate is non-overlapping with an orthographic projection of a respective voltage supply line on the base substrate.