LINK COORDINATION IN MULTI-LINK DEVICES
Abstract:
A system includes a memory and a processor communicatively coupled to the memory. The processor, in response to determining that a first number of transmissions over a first link with a first frequency has failed, selects a second link with a second frequency for transmission. The second frequency is lower than the first frequency. The processor also, in response to determining that a second number of transmissions over the second link has failed, one or more of (i) stop the transmissions over the second link or (ii) begins transmissions over a third link with a third frequency. The second number is greater than the first number.
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