An integrated circuit semiconductor device includes a substrate having a first surface and a second surface opposite to the first surface; a power via penetrating between the first surface and the second surface of the substrate; a cell part including a plurality of individual elements having different thicknesses inside the substrate, and a recess positioned between the individual elements; a signal wiring part on the first surface of the substrate and including an upper multilayer wiring layer connected to the power via; a power transmission network part under the second surface of the substrate and including a lower multilayer wiring layer connected to the power via; and an external connection terminal under the power transmission network part and connected to the lower multilayer wiring layer, wherein the substrate includes a plurality of regions having different thicknesses.