A monolithic 3D complementary field-effect transistor (FET) (CFET) circuit includes a first CFET structure and a second CFET structure in a logic circuit within a device layer. A first interconnect layer disposed on the device layer provides first and second input contacts and an output contact of a logic circuit. Each CFET structure includes an upper FET having a first type (e.g., P-type or N-type) on a lower FET having a second type (e.g., N-type or P-type). The FETs in the monolithic 3D CFET circuit may be interconnected to form a two-input NOR circuit or a two-input NAND circuit. Vertical access interconnects (vias) may be formed within the device layer to interconnect the FETs externally and to each other. The FETs may be formed as bulk-type transistors or SOI transistors.