DYNAMIC MEMORY MANAGEMENT APPARATUS AND METHOD FOR HLS
Abstract:
The present invention relates to a dynamic memory management apparatus and method for HLS, the apparatus at least comprising: several searching and caching modules and several modifying and writing-back modules, wherein the searching and caching modules are in connection with a DRAM storing module and a BRAM buffer, respectively, and the modifying and writing-back modules are in connection with the DRAM storing module and the BRAM buffer, respectively, wherein the BRAM buffer is for caching information about nodes on a search path and registering information about modification made to the nodes; the searching and caching module is for reading node data from the DRAM storing module according to received operators and node addresses, and writing the node data into the BRAM buffer; and the modifying and writing-back module reads the node data from the BRAM buffer and writes the node data back into the DRAM storing module. Aiming at the defect that the traditional operating system is directly transplanted to the FPGA and has low execution efficiency, the present invention utilizes the advantage of the large capacity of the DRAM on the FPGA to realize efficient dynamic memory allocation and deallocation, and improve the usability and code reusability of HLS.
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