A system for accessing a plurality of instruments embedded in a semiconductor device includes a hardware interface and a test controller for testing the semiconductor device or generating test patterns for the semiconductor device, wherein the test controller comprises an instrument connectivity language and a procedural description language configuration for operating the instruments. The test controller is configured to perform the steps of: testing at least one functionality of each of the plurality of instruments, thereby receiving a fault status of each of the plurality of instruments; and based on the fault status of the plurality of instruments, configuring a test block in the semiconductor device such that valid test patterns for the semiconductor device can be generated without updating the instrument connectivity language and procedural description language configuration.