Described are techniques for generating a supply voltage for an SRAM array using power switching logic. The power switching logic can generate the supply voltage using a first supply rail (supplying a higher voltage) during an active state and using a second supply rail (supplying a lower voltage) during a deep retention state. In some examples, a sensing and recovery (SR) unit is provided to sense a decrease in the second voltage, for instance, during the deep retention state. The SR unit can generate an additional voltage that modifies the supply voltage to be higher than the decreased second voltage, thereby reducing droop and/or noise in the second supply rail. The power switching logic, SR unit, and SRAM array can be co-located or distributed across a computer system. For instance, the power switching logic, SR unit, and SRAM array can be embedded within a System on Chip integrated circuit.