Invention Publication
- Patent Title: CIRCUIT DESIGN ADJUSTMENTS USING REDUNDANT NODES
-
Application No.: US18139882Application Date: 2023-04-26
-
Publication No.: US20240078366A1Publication Date: 2024-03-07
- Inventor: Eleonora TESTA , Luca Gaetano AMARU , Patrick Emmanuel VUILLOD
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Sunnyvale
- Main IPC: G06F30/323
- IPC: G06F30/323

Abstract:
The present disclosure describes systems and methods for adjusting a logic network. The method includes adding, to the logic network, a first redundant node and determining a first adjustment to a first node of the logic network within a transitive fanin of the first redundant node. The method also includes making the first adjustment to the first node based on determining that a first gain based on the first adjustment satisfies a threshold.
Information query