A method for execution by a Dynamic Random Access (DRAM) cell processing circuit in a read mode, includes receiving a pre-charge input and charging a bit-line operably coupled to a plurality of DRAM cells of a DRAM memory device, including a current DRAM cell, to a pre-charge voltage. The method continues by sensing a voltage change on the bit-line, where the sensing is based on a difference between a voltage stored on a DRAM cell capacitor of the current DRAM cell and the pre-charge voltage and generating a logic input for one of four voltage states for the current DRAM cell. The method then continues by supplying, supplying, based on the logic input, a corresponding logic voltage on the bit-line to refresh the voltage stored in the DRAM cell capacitor of the current DRAM cell.