Invention Publication
- Patent Title: SIGNALING OF TIME FOR COMMUNICATION BETWEEN INTEGRATED CIRCUITS USING MULTI-DROP BUS
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Application No.: US18515468Application Date: 2023-11-21
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Publication No.: US20240097937A1Publication Date: 2024-03-21
- Inventor: Helena Deirdre O'SHEA , Matthias SAUER , Jorge L. RIVERA ESPINOZA
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Main IPC: H04L12/413
- IPC: H04L12/413 ; H04L12/40

Abstract:
Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.
Public/Granted literature
- US12284054B2 Signaling of time for communication between integrated circuits using multi-drop bus Public/Granted day:2025-04-22
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