A memory device includes first registers configured to store row addresses second registers configured to store an access count of each of the row addresses and generate a reference value flag signal when the access count is higher than a reference value. The memory device also includes a target row refresh controller configured to select one of the row addresses as a first target row address in response to the reference value flag signal, perform a first refresh operation on at least one first row address adjacent to the first target row address, randomly select one of the row addresses as a second target row address, and perform a second refresh operation on at least one second address adjacent to the second target row address. The second refresh operation may be performed when the reference value flag signal indicates that the access count is not greater than the reference value.