Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments for supporting processor capabilities may be configured to support increased efficiency in utilization of a micro-operations cache (UC) of a processor. Various example embodiments for supporting increased efficiency in utilization of a UC of a processor may be configured to support increased efficiency in utilization of the UC of the processor based on configuration of the processor such that UC lines created by a prediction window (PW) during execution of a set of instructions by the processor are not invalidated on misprediction of a branch instruction in the set of instructions.