A semiconductor memory device includes a cell substrate, a plurality of gate electrodes sequentially stacked on the cell substrate and extending in a first direction, first and second channel structures extending in a second direction different from the first direction and penetrating the plurality of gate electrodes, and a bit line disposed on the plurality of gate electrodes. The first and second channel structures each include a ferroelectric layer, a channel layer, a gate insulating layer and a back gate electrode, which are sequentially disposed on side walls of the plurality of gate electrodes. The first channel structure and the second channel structure are adjacent to each other in the first direction and share a bit line.