An apparatus and method for implementing a Level 0 cache within a cache subsystem. For example, one embodiment of a processor comprises: a cache subsystem comprising a Level-0 cache; a scheduler to schedule a load operation indicating data to be loaded; and a load hit predictor to predict whether the data indicated by the load operation is stored in the LO cache and to generate a wakeup signal to the scheduler in response to predicting that the data is stored in the LO cache. Some implementations perform store forwarding in response to load operations using a multi-step approach in which a partial linear address check is performed to determine load operations which are eligible for store forwarding. A full address check is performed for those load operations which are eligible in which the address of the load is compared against the address of a youngest older store operation. Mini-MOB implementations are also described including a stale data watchdog function and wakeup signal to schedule dependent operations.