- 专利标题: TRANSISTOR ISOLATION STRUCTURES
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申请号: US18409421申请日: 2024-01-10
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公开(公告)号: US20240145579A1公开(公告)日: 2024-05-02
- 发明人: Yu-Yun PENG , Fu-Ting YEN , Keng-Chu LIN
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsinchu
- 主分类号: H01L29/66
- IPC分类号: H01L29/66 ; H01L29/06
摘要:
The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.
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