- 专利标题: Integrated Resistor Network and Method for Fabricating the Same
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申请号: US18512419申请日: 2023-11-17
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公开(公告)号: US20240162896A1公开(公告)日: 2024-05-16
- 发明人: Oren Shlomo
- 申请人: Infineon Technologies LLC
- 申请人地址: US CA San Jose
- 专利权人: Infineon Technologies LLC
- 当前专利权人: Infineon Technologies LLC
- 当前专利权人地址: US CA San Jose
- 主分类号: H03K5/1252
- IPC分类号: H03K5/1252 ; G01K7/18 ; G01K7/20 ; G01R19/25 ; G05F1/648 ; G11C7/02 ; G11C7/10 ; G11C7/14 ; G11C7/20 ; H03K5/153 ; H03K5/19 ; H03K5/24 ; H03K17/22 ; H03K17/24
摘要:
A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n-1, and the third number is 1, the total number of resistors is 2n.
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