Invention Publication
- Patent Title: WRITE STREAMING WITH CACHE WRITE ACKNOWLEDGMENT IN A PROCESSOR
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Application No.: US18425165Application Date: 2024-01-29
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Publication No.: US20240168883A1Publication Date: 2024-05-23
- Inventor: Abhijeet Ashok Chachad , Timothy David Anderson , David Matthew Thompson
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Main IPC: G06F12/0842
- IPC: G06F12/0842 ; G06F1/14 ; G06F9/38 ; G06F9/54 ; G06F12/0811 ; G06F12/0888

Abstract:
In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory controller. The memory controller has a memory pipeline. The memory controller is coupled to control the cache memory and communicatively coupled to the processor core. The memory controller is configured to receive the memory write requests from the processor core; schedule the memory write requests on the memory pipeline; and contemporaneously with scheduling respective ones of the memory write requests on the memory pipeline, send to the processor core a write acknowledgment confirming that writing of a data payload of the respective memory write request to the cache memory has completed.
Information query
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