Invention Publication
- Patent Title: ERROR-DETECTION SCHEMES FOR ANALOG CONTENT-ADDRESSABLE MEMORIES
-
Application No.: US17983050Application Date: 2022-11-08
-
Publication No.: US20240170082A1Publication Date: 2024-05-23
- Inventor: Ron M. Roth , Catherine Graves
- Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Applicant Address: US TX Spring
- Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Current Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Current Assignee Address: US TX Spring
- Main IPC: G11C29/10
- IPC: G11C29/10 ; G11C15/04 ; G11C27/00

Abstract:
Examples of the presently disclosed technology provide new circuits for detecting errors in aCAMs with improved efficiency. Specifically designed around the structure and operation of aCAM arrays, these circuits include counter sub-circuits electrically connected to match lines of aCAM rows such that the counter sub-circuits receive match-related signals output from aCAM rows. The value stored by a counter sub-circuit may change in response to receiving a match signal, and may remain the same in response to receiving a mismatch signal. As will be described in greater detail below, the stored value of the counter sub-circuit may be used to detect/identify an error in its associated aCAM row after a set of (specially-computed) error-detection input vectors are sequentially applied to the circuit.
Public/Granted literature
- US11978523B1 Error-detection schemes for analog content-addressable memories Public/Granted day:2024-05-07
Information query