Invention Publication
- Patent Title: Wiring Layer And Manufacturing Method Therefor
-
Application No.: US18436245Application Date: 2024-02-08
-
Publication No.: US20240186331A1Publication Date: 2024-06-06
- Inventor: Yutaka OKAZAKI , Tomoaki Moriwaka , Shinya Sasagawa , Takashi Ohtsuki
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Kanagawa-ken
- Priority: JP 14202820 2014.10.01
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/768 ; H01L23/532 ; H01L29/66 ; H01L29/786

Abstract:
To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.
Public/Granted literature
- US12183747B2 Wiring layer and manufacturing method therefor Public/Granted day:2024-12-31
Information query
IPC分类: