A system on chip includes a core configured to maintain a clock gating state; a plurality of header switch circuits configured to deliver a supply voltage, which is reduced from an external supply voltage, to the core in response to a plurality of control signals; and a voltage regulator configured to monitor the supply voltage, change logic levels of the plurality of control signals according to a difference level corresponding to a difference between the supply voltage and a preset target voltage, and output the plurality of control signals of which the logic levels have been changed to the plurality of header switch circuits.