A semiconductor memory device may include an active pattern on a substrate and at least partially surrounded by a device isolation pattern, a gate electrode that crosses the active pattern in a first direction parallel to a bottom surface of the substrate, the gate electrode including lower and upper portions, and a side-capping pattern on a top surface of the lower portion of the gate electrode. The side-capping pattern may be on a side surface of the upper portion of the gate electrode, and a top surface of the side-capping pattern may be located at a level lower than an uppermost surface of the device isolation pattern, relative to the bottom surface of the substrate where the bottom surface of the substrate is a base reference layer.