A semiconductor memory device includes a substrate including a plurality of active regions in a memory cell region, a plurality of bit line structures extending in parallel with each other in a first horizontal direction in the memory cell region, a plurality of buried contacts respectively and electrically connected to the active regions and partially filling a space between the bit line structures, a plurality of lower landing pads in the space between the bit line structures and respectively on the buried contacts, a landing pad insulating structure in contact with the bit line structures and the lower landing pads and including a plurality of landing pad holes, a plurality of upper landing pads respectively filling the landing pad holes and respectively connected to the lower landing pads, and a plurality of capacitor structures.