A memory device may include multiple memory cells configured to store data. The memory device may also include multiple digit lines that carry data to and from a respective memory cell. The memory device may include multiple sense amplifiers each selectively coupled to respective digit lines and including first and second transistors and first and second gut nodes coupled to the first and second transistors, respectively. Each sense amplifier may amplify a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based on respective charges the digit lines, where a gain of the amplification is based on a negative voltage supplied to the sense amplifier and/or negative digit line write back operations.