Invention Publication
- Patent Title: MANAGING ALLOCATION OF SUB-BLOCKS IN A MEMORY SUB-SYSTEM
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Application No.: US18402306Application Date: 2024-01-02
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Publication No.: US20240231641A1Publication Date: 2024-07-11
- Inventor: Yu-Chung Lien , Tomer Tzvi Eliash , Zhenming Zhou
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/1009

Abstract:
A processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells associated with a first sub-block of a first die of the memory device, wherein each die of the memory device comprises a plurality of sub-blocks. The processing device identifies, based on a first predefined value, a second sub-block of a second die of the memory device on which to perform a second programming operation, wherein the first predefined value is a shift in an index value of the first sub-block of the first die of the memory device. The processing device further performs the second programming operation on a second set of cells associated with the second sub-block of the second die, wherein the second sub-block of the second die is associated with a different index value than the first sub-block of the first die.
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