A semiconductor memory device includes structures including insulation layers and semiconductor layers alternately stacked in a vertical direction, the structures being spaced apart from one another in a horizontal direction; an interlayer insulation layer between the structures; gate electrodes respectively in gate trenches passing through the interlayer insulation layer in the vertical direction, between the structures, the gate electrodes connected to the semiconductor layers; and vertical insulation layers respectively on sidewalls of the gate trenches, wherein each gate electrode includes first portions overlapping the insulation layers in the horizontal direction and second portions overlapping the semiconductor layers in the horizontal direction, and a first width of each first portion in the horizontal direction is greater than a second width of each second portion in the horizontal direction.