发明公开
- 专利标题： POWER AMPLIFIER
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申请号： US18566330申请日： 2021-12-08
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公开(公告)号： US20240282725A1公开(公告)日： 2024-08-22
- 发明人: Yoshinobu SASAKI , Katsuya KATO , Kazuya YAMAMOTO
- 申请人： Mitsubishi Electric Corporation
- 申请人地址： JP Tokyo
- 专利权人： Mitsubishi Electric Corporation
- 当前专利权人： Mitsubishi Electric Corporation
- 当前专利权人地址： JP Tokyo
- 国际申请： PCT/JP2021/045054 2021.12.08
- 进入国家日期： 2023-12-01
- 主分类号： H01L23/66
- IPC分类号： H01L23/66 ; H03F1/56 ; H03F3/60
摘要：
A FET chip (T1) includes a FET cell (CL1,CL2), a fundamental wave gate pad (GP1,G12) and a second harmonic gate pad (GP3) separated from each other, and gate wiring (GB1,GB2) connecting a gate electrode (G1,G2) of the FET cell (CL1,CL2) to the fundamental wave gate pad (GP1,G12) and the second harmonic gate pad (GP3). A pre-match chip (P1) includes a fundamental wave pre-match circuit (PA1,PA2) and a second harmonic trap circuit (PA3). A fundamental wave wire (W21,W22) connects the fundamental wave pre-match circuit (PA1,PA2) and the fundamental wave gate pad (GP1,G12). A second harmonic wire (W31,W32) connects the second harmonic trap circuit (PA3) and the second harmonic gate pad (GP3).
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