A system includes a memory device having a plurality of blocks. A first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory. A processing device, operatively coupled to the memory device, determines that a first block of a set of blocks of the first subset is a bad block, wherein the first block is located in a first plane of the memory device. The processing device converts a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a second plane of the memory device, and wherein the second plane is neighboring the first plane.