MATRIX MULTIPLICATION IN A DYNAMICALLY SPATIALLY AND DYNAMICALLY TEMPORALLY DIVIDABLE ARCHITECTURE
Abstract:
A data processing apparatus includes input circuitry that receives a matrix having values in a first format. Output circuitry outputs the matrix having the values in a second format while adjustment circuitry performs a modification of the matrix from the first format to the second format. The second format is computationally contiguous in respect of a data processing apparatus having the first and second vector registers both configured to be dynamically spatially and dynamically temporally divided, performing a matrix multiplication.
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