- 专利标题: HYBRID BONDING TECHNOLOGY FOR STACKING INTEGRATED CIRCUITS
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申请号: US18758167申请日: 2024-06-28
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公开(公告)号: US20240355784A1公开(公告)日: 2024-10-24
- 发明人: Kuo-Ming Wu , Ching-Chun Wang , Dun-Nian Yaung , Hsing-Chih Lin , Jen-Cheng Liu , Min-Feng Kao , Yung-Lung Lin , Shih-Han Huang , I-Nan Chen
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsinchu
- 主分类号: H01L25/065
- IPC分类号: H01L25/065 ; H01L23/00 ; H01L23/48 ; H01L23/528 ; H01L23/532 ; H01L25/00
摘要:
A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via (TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.
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