A method of fabricating a memory device includes forming a plurality of first nanostructures, a plurality of second nanostructures, a plurality of third nanostructures, and a plurality of fourth nanostructures; separating the plurality of first nanostructures and the plurality of second nanostructures with a dielectric fin structure; forming a first gate structure wrapping around each of the first nanostructures except for a sidewall that is in contact with the dielectric fin structure; forming a second gate structure wrapping around each of the second nanostructures except for a sidewall that is in contact with the dielectric fin structure; and forming a first interconnect structure coupled to one of the first gate structure or second gate structure. The dielectric structure also extends along the first lateral direction. The first and second gate structures extend along a second lateral direction perpendicular to the first lateral direction.