Invention Application
- Patent Title: PRE-PROGRAM PASS TO REDUCE SYSTEM BUFFER REQUIREMENT WHEN PROGRAMMING QUAD-LEVEL CELL (QLC) MEMORY
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Application No.: US18636584Application Date: 2024-04-16
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Publication No.: US20240393977A1Publication Date: 2024-11-28
- Inventor: Ratna Priyanka Sistla , Dan Xu , Tomoko Ogura Iwasaki , Caixia Yang , Lee-eun Yu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
A memory device includes a memory array configured as quad-level cell (QLC) memory and a control logic operatively coupled to the memory array. The control logic identifies a first two bits of particular pages of a QLC logical state. The control logic causes memory cells of the memory array to be coarse programmed with a threshold voltage distribution of a multi-level cell (MLC) logical state corresponding to the first two bits. The control logic reads the MLC logical state from the memory cells and a second two bits from a cache buffer to determine the QLC logical state. The control logic causes the memory cells to be further coarse programmed with a QLC threshold voltage distribution corresponding to the QLC logical state.
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