In one implementation a processor has an instruction fetch circuit fetching instructions, the instruction fetch circuit having an input and an output and a decode circuit to decode the fetched instructions, the decode circuit having a first and second input, and an output, wherein the decode circuit first input is coupled to the instruction fetch circuit output receiving the fetched instructions, and an execution circuit executing the decoded fetched instructions, the execution circuit having an input coupled to the decode circuit output to receive the decoded fetched instructions, and a switch instruction circuit (SIC) to detect and execute switch instructions of the fetched instructions, the SIC having an input and an output, wherein the SIC input is coupled to the instruction fetch circuit output to receive the fetched instructions, wherein the SIC output is coupled to the decode circuit second input and the instruction fetch circuit input.